Supplemental Material for Fall 2015 Computer Literacy

Sample instructions for creating SOF

1. File > New Project Wizard, Next
2. Add Files, Next
3. Name of this Project: DoorOpener
4. Device Family: Cyclone V (E/GX/GT/SX/SE/ST)
5. Devices: Cyclone V SE Mainstream
6. Select device: 5CSEMA5F31C6, Next, Next
7. Simulation Tool Name: ModelSim, Format: VHDL
8. Uncheck "Run gate-level simulation automatically after compilation", Next

1. File > New > Block Diagram/Schematic File
2. Finish
3. File | New | Block Diagram/Schematic File", OK
4. File | Save As
5. Default name is ok; Save
6. Enter symbols to match
7. Add to project with: Project | Add Current File to Project
8. Compile the design: Processing | Start Compilation
9. Create system in HDL VHDL with File | Create/Update | Create HDL Design File from Current File; be sure to select the bdf first
10. Select "VHDL" as File type; click on OK
11. Open your newly created VHDL file: File | Open File, DoorOpener.vhd
12. Select DoorOpen.vhd; Add to project with: Project | Add Current File to Project
13. Remove the bdf file from the Project, but do NOT delete the file from the filesystem: Project | Add/Remove Files from Project; select DoorOpener.bdf and delete
14. Note: If you did not select the device, do so now with: Assignments | Device
15. Compare the settings via Assignment | Settings, EDA Tool Settings, Simulation with
16. Select Simulation, "More EDA Netlist Writer Settings"
17. Turn on Generate netlist for functional simulation only; you need to click/double click on "Off" in order to select "On"; select OK
18. 
19. Note: I did not use "user compiled simulation library"
20. Note: I also did not change "More NativeLink Settings"
21. Check EDA Tools setting in: Tools | Options | EDA Tool Options
22. ModelSim: c:\Modeltech_pe_edu_10.4a\win32pe_edu\
23. ModelSim-Altera: c:\altera\13.1\modelsim_ase\win32aloem\
24. Compile the circuit for functional simulation: Processing | Start | Start Analysis & Elaboration
25. Create testbench: Processing | Start | Start Test Bench Template Writer
26. Note: You may need to select "all files"; Open file in simulation\modelsim, called DoorOpener.vht
27. After adding simulation statements, change settings to include your testbench: Assignments | Settings, EDA Tool Settings, Simulation
28. Select radio button "Compile test bench", click on "Test Benches", then "New"
29. Choose testbench name, here is "dooropenertest", add "dooropener.vht"; click on "..." to select vht file
30. Click "Add", and then "OK". and then "ok" on previous menu, and finally "ok" on the Settings menu
31. 
32. Select the vht file, then add to the project with Project | Add Current File to Project
33. After anytime you change the simulation (or after creating), must prepare with: Processing | Start | Start Analysis & Elaboration
34. To run the simulation: Tools | Run Simulation Tool | RTL Simulation
35. Now, from the ModelSim program, expand "Model" by clicking on the plus sign
36. Simulate | Start Simulation
37. Select the testbench entry, dooropener_vhd_tst, click "ok"
38. If you were using actual board pins, you would assign them with: Assignments | Pin Planner
39. Tools > Programmer
40. Click Auto Detect
41. Select 5CSEMA5 and click OK
42. Select SCSEMA5F31; click Change File
43. Note: the FPGA is the SCSEMA5 icon
44. Note: the HPS is the SOCVHPS icon
45. Click on Program/Configure tab
46. Press Start button

Optional: Test with stand alone ModelSim PE Student Edition, 10.4a

1. Change to the current directory with: File | Change Directory
2. Create new library: File | New | Library Use default name of "work"
3. Compile simulation file created previously: Compile | Compile simulation\modelsim\ DoorOpener.vht
4. Verify that there are no errors in the command line interupter
5. Optional: compile the cli with: vcom -reportprogress 300 -work work c:/Users..../simulation/modelsim/DoorOpenerTest.vht