Note: Refers to Chapter 4 of the SoC User Manual
Automatically generated files
- Quartus II project file (.qpf)
- Quartus II setting file (.qsf>
- Top-level design file (.v)
- Synopsis design contraints file (.sdc)
- Pin assignment document (.htm)>
Major files:
Top level design file contains a top-level Verilog HDL wrapper to add custom design and logic.
The Quartus II setting file contains FPGA device type, top-level pin assignment and I/O standard for each user-defined I/O pin.
To run System Builder, locate directory of installation; located at: Tools\SystemBuilder\SystemBuilder.exe
Use Quartus II to load the SOF (should be in the directory as the automatically generated files
Within Quartus II you must compile the project to create the SOF: Processing | Start Compilation
Download the SOF via Tools | Programmer
Example using DE2 Board