DE1-SOC FPGA

Table 3-5 Pin Assignment of Clock Inputs

Table 3-6 Note: re: "DE1-SoCUserManual", when the switch is in the down position (towards the edge of the board), it generates a low logic level to the FPGA.
When the switch is set to the UP position, a high logic level is generated to the FPGA. Pin Assignment of Slide Switches
Image depicting SW0 as closed SW0 in Closed Position

Table 3-7 Pin Assignment of Push-buttons

Table 3-8 Pin Assignment of LEDs

Table 3-9 Pin Assignment of 7 segment displays

Table 3-11
Note: Ground is 6th pin (starting from 1), on the right side
VCC5 is the 6th pin (starting from 1), on the left side
Both of these pins do NOT have a FPGA pin assignment
GPIO Header 5 Volt and Ground
Pin Assignment of GPIO 0 Expansion Header

Table 3-11
Note: Ground is 6th pin (starting from 1), on the right side
VCC5 is the 6th pin (starting from 1), on the left side
Both of these pins do NOT have a FPGA pin assignment Pin Assignment of GPIO 1 Expansion Headers

Table 3-12 Pin Assignment of Audio CODEC

Table 3-13 Pin Assignment of I2C Bus

Table 3-16 Pin Assignment of VGA

Table 3-17 Pin Assignment of TV Decoder

Table 3-18 Pin Assignment of IR Receiver

Table 3-19 Pin Assignment of IR Emitter LED

Table 3-20 Pin Assignment of SDRAM

Table 3-21 Pin Assingment of PS/2

Table 3-22 Pin Assignment of ADC

Table 3-23 Pin Assignment of LEDs, Switches and Push-Buttons

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