Monitor Program Basics

Term
Definition
amp
Altera Monitor Program
Extension
Type
s
Assembly language source code
lder system integration tools to automate the configuring of processor features and to generate a hardware design for your device.

Architecture function units

  • Register file
  • Arithmetic logic unit (ALU)
  • Interface to custom instruction logic
  • Exception controller
  • Internal or exteral interrupt controller
  • Instruction bus
  • Data bus

Excellent resource to the entire SOPC building cycle
Another resource to the SOPC building cycle
Note: Qsys is the new name for SOPC; First SOPC with Qsys

Reference files (from c:\altera\13.1\University_Program\Computer_Systems\DE1-SoC\DE1-SoC_Computer\app_software) that the default sof for Monitor Program is built from.
Warning: These may not match your configuration or installation file system!
In addition, Symbolic names are NOT consistent!

Sample Assembly language programs.
Note: When you "add" an .s assembly language program, before it can be used you press F5 to compile and load; the compile actually can be run in the Nios II command line as:

Note:This assumes the source file of getting_started.s, and a path of /Users/steve/Src/ProjectName

nios2-elf-as --gstabls -I "C:/altera/13.1/nios2eds/components/altera_nios2/sdk/inc" -I "C:/Users/steve/Src/ProjectName" "C:/Users/steve/Src/ProjectName/getting_started.s" -o "C:/Users/steve/Src/Projectname/getting_started.s.o"
Followed by:
nios2-elf-ld --defsym nasys_program_mem=0x0 --defsym nasys_data_mem=0x0 --section-start .exceptions=0x20 --section-start .reset=0x0 -e _start -u _start --script "C:/altera/13.1/University_Program/Monitor_Program/build/nios_as_build.ld" -g -o "C:/Users/steve/src/ProjectName/getting_started.elf" "C:/Users/steve/src/ProjectName/getting_started.s.o"
Also, you must compile and load in order to see the source within the Disassembly window.

Symbol Address Map

Pin Assignment Map

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