Is equivalent to a microcontroller of "computer on a chip", including a processor, periphals and memory on a single chip.
Nios II consists of Nios II processor core, on-chip peripherals, on-chip memory, interface to off-chip memory on a single Altera device
Use Altera's Qsys and SOPC Builder system integration tools to automate the configuring of processor features and to generate a hardware design for your device.
Architecture function units
Nios II has a Reduced Instruction Set Computer (RISC) architecture. Arithmetic and logic operations are performed on operands in the general purpose registers. Data is moved between the memory and registers by Load and Store instructions
All words are 32 bits long; registers are all 32 bits long. Instructions can read and write words (32 bits), halfwords (16 bits), and bytes (8 bits). Byte addresses are 32 bit words that are defined as little-endian or big-endian. Little-endian have the lower byte addresses used for the less significant byte (rightmost byte).
Processor Implementation: The Nios II architecture describes an instruction set, not the specific hardware implemention; a functional unit can be implemented in hardware, emulated in software, or omitted entirely.
Includes both instruction and data caches implemented in FPGA memory blocks
Nios II uses separate instruction and data busses (known as the Harvard architecture)
Instructions are i-type, r-type and j-type
Currently floating-point operations are not directly supported